Altera Arria V GZ Avalon-ST - Manual (Page 64)

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
Figure 5-9: 128-Bit Avalon-ST rx_st_data Cycle Definition for 3-Dword Header TLPs with Qword
Aligned Addresses
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for TLPs
with a three dword header and qword aligned addresses. The assertion of
rx_st_empty
in a
rx_st_eop
cycle, indicates valid data on the lower 64 bits of
rx_st _data
.
pld_clk
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_bardec[7:0]
rx_st_sop
rx_st_eop
rx_st_empty
data3
header2 data2
header1 data1 data
header0 data0 data
01
5-12 Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
UG-01127_avst
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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