Altera Arria V GZ Avalon-ST - Manual (Page 221)

• The chaining DMA writes the
EPLast
bit of the Chaining DMA Descriptor Tableafter
completing the data transfer for the first and last descriptors.
• The chaining DMA issues an MSI when the last descriptor has completed.
• The data written back to BFM is checked against the data that was read from the BFM.
• The driver programs the chaining DMA to perform a test that demonstrates downstream access
of the chaining DMA Endpoint memory.
Note: Edit this file if you want to add your own custom PCIe transactions. Insert your own custom
function after the
find_mem_bar
function. You can use the functions in the BFM Procedures and
Functions section.
Related Information
• Chaining DMA Descriptor Tables on page 17-13
• BFM Procedures and Functions on page 17-31
DMA Write Cycles
The procedure
dma_wr_test
used for DMA writes uses the following steps:
1. Configures the BFM shared memory. Configuration is accomplished with three descriptor tables
described below.
Table 17-11: Write Descriptor 0
Offset in BFM in
Shared Memory
Value
Description
DW0 0x810 82 Transfer length in dwords and control bits as described in
Bit Definitions for the Control Field in the DMA Write
Control Register and DMA Read Control Register.
DW1 0x814 3 Endpoint address
DW2 0x818 0 BFM shared memory data buffer 0 upper address value
DW3 0x81c 0x1800 BFM shared memory data buffer 1 lower address value
Data
Buffer 0
0x1800 Increment by 1
from 0x1515_
0001
Data content in the BFM shared memory from address:
0x01800–0x1840
UG-01127_avst
2014.12.15
DMA Write Cycles 17-17
Testbench and Design Example Altera Corporation
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