Altera Arria V GZ Avalon-ST - Manual (Page 113)

Physical Layout of Hard IP in Arria V GZ Devices
Arria V GZ devices include one Hard IP for PCI Express IP core. The following figures illustrate the
placement of the PCIe IP core, transceiver banks, and channels.
Figure 5-44: Physical Layout of Hard IP in Arria V GZ Devices
6 Ch
6 Ch
PCIe
Hard
IP
GXB_R2 GXB_L2
GXB_L1
GXB_L0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
6 Ch
6 Ch GXB_R1
GXB_R0
24
Channels
6 Ch
6 Ch
36 Channels
Notes:
1. 12-channel devices use banks L0 and L1.
2. All channels capable of backplane support up to 12.5 Gbps.
Refer to Transceiver Architecture in Arria V Devices for comprehensive information on the number of
Hard IP for PCIe IP cores available in various Arria V GZ packages.
Refer to Channel Utilization for Data and Clock Routing in Arria V GZ and Stratix V Devices for
additional information about channel and PLL utilization.
Related Information
• Transceiver Architecture in Arria V Devices
• Pin-Out Files for Altera Devices
UG-01127_avst
2014.12.15
Physical Layout of Hard IP in Arria V GZ Devices 5-61
Interfaces and Signal Descriptions Altera Corporation
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