Altera Arria V GZ Avalon-ST - Manual (Page 55)

Signal Direction Description
For 128-bit data, only bit 0 applies; this bit indicates whether the
upper qword contains data. For 256-bit data single packet per
cycle mode, both bits are used to indicate whether 0-3 upper
qwords contain data, resulting in the following encodings for the
128-and 256-bit interfaces:
• 128-Bit interface:
•
rx_st_empty
= 0,
rx_st_data[127:0]
contains valid data
•
rx_st_empty = 1
,
rx_st_data[63:0]
contains valid data
• 256-bit interface: single packet per cycle mode
•
rx_st_empt y
= 0,
rx_st_data[255:0]
contains valid
data
•
rx_st_empty
= 1,
rx_st_data[191:0]
contains valid data
•
rx_st_empty
= 2,
rx_st_data[127:0]
contains valid
data
•
rx_st_empty
= 3,
rx_st_data[63:0]
contains valid data
• For 256-bit data, when you turn on Enable multi ple packets
per cycle, the following correspondences apply:
• bit 1 applies to the eop occurring in rx_st_data[255:128]
• bit 0 applies to the eop occurring in rx_st_data[127:0]
• When the TLP ends in the lower 128 bits, the following
equations apply:
•
rx_st_eop[0]=1 & rx_st_empty[0]=0
,
rx_st_
data[127:0]
contains valid data
•
rx_st_eop[0]=1 & rx_st_empty[0]=1
,
rx_st_
data[63:0]
contains valid data,
rx_st_data[127:64]
is
empty
• When TLP ends in the upper 128bits, the following equations
apply:
•
rx_st_ eop[1]=1 & rx_st_empty[1]=0
,
rx_st_
data[255:128]
contains valid data
•
rx_st_eop[1]=1 & rx_st_empty[1]=1
,
rx_st_
data[191:128]
contains valid data,
rx_st_
data[255:192]
is empty
rx_st_ready
Input Indicates that the Application Layer is ready to accept data. The
Application Layer deasserts this signal to throttle the data stream.
If
rx_st_ready
is asserted by the Application Layer on cycle
, then
readyLatency
> is a ready cycle, during which
the Transaction Layer may assert
valid
and transfer data.
The RX interface supports a
readyLatency
of 2 cycles.
UG-01127_avst
2014.12.15
Avalon‑ST RX Interface 5-3
Interfaces and Signal Descriptions Altera Corporation
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