Altera Arria V GZ Avalon-ST - Manual (Page 63)

Figure 5-8: 4-Bit Avalon-ST Interface Back-to-Back Transmission
The following figure illustrates back-to-back transmission on the 64-bit Avalon-ST RX interface with no
idle cycles between the assertion of
rx_st_eop
and
rx_st_sop
.
pld_clk
rx_st_data[63:0]
rx_st_sop
rx_st_eop
rx_st_ready
rx_st_valid
C. C. C. C. CCCC0089002... C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C C
Related Information
• Transaction Layer Packet (TLP) Header Formats on page 19-1
• Avalon Interface Specifications
UG-01127_avst
2014.12.15
Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface 5-11
Interfaces and Signal Descriptions Altera Corporation
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