Altera Arria V GZ Avalon-ST User Manual
Page 15
Getting Started with the Arria V GZ Hard IP for
PCI Express
2
2014.12.15
UG-01127_avst
This section provides instructions to help you quickly customize, simulate, and compile the Arria V GZ
Hard IP for PCI Express IP Core. When you install the Quartus II software you also install the IP Library.
This installation includes design examples for Hard IP for PCI Express under the
altera_pcie/
directory.
After you install the Quartus II software, you can copy the design examples from the
altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/
directory. This walkthrough uses the
Gen1 ×8 Endpoint, pcie_de_gen1_x8_ast128.qsys. The following figure illustrates the top-level modules
of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine, labeled APPS
in the following figure, and a Root Port model. The simulation can use the parallel PHY Interface for PCI
Express (PIPE) or serial interface.
Figure 2-1: Testbench for an Endpoint
APPS
altpcied_
Hard IP for PCI Express Testbench for Endpoints
Avalon-ST TX
Avalon-ST RX
reset
status
Avalon-ST TX
Avalon-ST RX
reset
status
DUT
altpcie_
Root Port Model
altpcie_tbed_
PIPE or
Serial
Interface
Root Port BFM
altpcietb_bfm_rpvar_64b_x8_pipen1b
Root Port Driver and Monitor
altpcietb_bfm_vc_intf
Note: The Quartus II release automatically creates a simulation log,
altpcie_monitor_
log.log
, file in your simulation directory. If you have an existing 13.1 or older design, you must
regenerate it in the current release in order to simulate. Regeneration is necessary to create the
supporting monitor file the generates
altpcie_monitor_
. Refer to
Understanding Simulation Log File Generation for details.
Altera provides example designs to help you get started with the Arria V GZ Hard IP for PCI Express IP
Core. You can use example designs as a starting point for your own design. The example designs include
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