Legacy interrupts – Altera Arria V GZ Avalon-ST User Manual
Page 151
Figure 8-7: MSI-X PBA Table
Pending Bits 0 through 63
Pending Bits 64 through 127
Pending Bits ((N - 1) div 64) × 64 through N - 1
QWORD 0
QWORD 1
QWORD (( N - 1) div 64)
Base
Address
Pending Bit Array (PBA)
Base + 1 × 8
Base + ((N - 1) div 64) × 8
4. The IRQ Processor reads the entry in the MSI-X table.
a. If the interrupt is masked by the
Vector_Control
field of the MSI-X table, the interrupt remains in
the pending state.
b. If the interrupt is not masked, IRQ Processor sends Memory Write Request to the TX slave
interface. It uses the address and data from the MSI-X table. If
Message Upper Address
= 0, the
IRQ Processor creates a three-dword header. If the
Message Upper Address > 0
, it creates a 4-
dword header.
5. The host interrupt service routine detects the TLP as an interrupt and services it.
Related Information
•
•
Legacy Interrupts
Legacy interrupts are signaled on the PCIe link using message TLPs. The message TLPs are generated
internally by the Arria V GZ Hard IP for PCI Express. The
app_int_sts
input port controls interrupt
generation. The assertion of
app_int_sts
causes an
Assert_INTA
message TLP to be generated and sent
upstream. Deassertion of
app_int_sts
causes a
Deassert_INTA
message TLP to be generated and sent
upstream. To use legacy interrupts, you must clear the
Interrupt Disable
bit, which is bit 10 of the
Command
register. Then, turn off the
MSI Enable
bit.
The following figure illustrates interrupt timing for the legacy interface. In this figure the assertion of
app_int_sts
instructs the Hard IP for PCI Express to send a
Assert_INTA
message TLP.
Figure 8-8: Legacy Interrupt Assertion
clk
app_int_sts
app_int_ack
The following figure illustrates the timing for deassertion of legacy interrupts. The assertion of
app_int_sts
instructs the Hard IP for PCI Express to send a
Deassert_INTA
message.
8-6
Legacy Interrupts
UG-01127_avst
2014.08.18
Altera Corporation
Interrupts