Altera Arria V GZ Avalon-ST - Manual (Page 164)

• Avalon Interface Specifications
Clocks and Reset
The PCI Express Base Specification requires an input reference clock, which is called
refclk
in this design.
The PCI Express Base Specification stipulates that the frequency of this clock be 100 MHz.
The PCI Express Base Specification also requires a system configuration time of 100 ms. To meet this
specification, IP core includes an embedded hard reset controller. This reset controller exits the reset state
after the I/O ring of the device is initialized.
Related Information
• Clock Signals on page 5-33
• Reset, Status, and Link Training Signals on page 5-34
Local Management Interface (LMI Interface)
The LMI bus provides access to the PCI Express Configuration Space in the Transaction Layer.
Related Information
LMI Signals on page 5-44
Hard IP Reconfiguration
The PCI Express reconfiguration bus allows you to dynamically change the
read-only
values stored in
the Configuration Registers.
Related Information
Hard IP Reconfiguration Interface on page 5-54
Transceiver Reconfiguration
The transceiver reconfiguration interface allows you to dynamically reconfigure the values of analog
settings in the PMA block of the transceiver. Dynamic reconfiguration is necessary to compensate for
process variations.
Related Information
Transceiver PHY IP Reconfiguration on page 16-1
10-4 Clocks and Reset
UG-01127_avst
2014.08.18
Altera Corporation IP Core Architecture
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