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Altera Arria V GZ Avalon-ST User Manual

Page 42

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Parameter

Value

Description

Enable configu‐

ration via PCI

Express (CvP)

On/Off

When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For

more information about CvP, click the Configuration via

Protocol (CvP) link below. CvP is not supported for Gen3

variants.

Enable credit

consumed

selection port tx_

cons_cred_sel

On/Off

When you turn on this option, the core includes the

tx_cons_

cred_sel

port. This parameter does not apply to the Avalon-

MM interface.

Enable Configu‐

ration bypass

(CfgBP)

On/Off

When On, the Arria V GZ Hard IP for PCI Express bypasses

the Transaction Layer Configuration Space registers included

as part of the Hard IP, allowing you to substitute a custom

Configuration Space implemented in soft logic.
This parameter is not available for the Avalon-MM IP Cores.

Enable Hard IP

Reconfiguration

On/Off

When On, you can use the Hard IP reconfiguration bus to

dynamically reconfigure Hard IP read-only registers. For more

information refer to Hard IP Reconfiguration Interface. This

parameter is not available for the Avalon-MM IP Cores.

Enable Hard IP

completion tag

checking

On/Off

When enabled, the Hard IP can use 32 or 64 tags for

completions and validates completion tags. When disabled,

the Hard IP can use up to 256 tags. The Application Layer

logic must validate completion tags.

Enable Hard IP

reset pulse at

power-up when

using the soft

reset controller

On/Off

When On, the soft reset controller generates a pulse at power

up to reset the Hard IP. This pulse ensures that the Hard IP is

reset after programming the device, regardless of the behavior

of the dedicated PCI Express reset pin,

perstn

. This option is

available for Gen2 and Gen3 designs that use a soft reset

controller.

Related Information

Throughput Optimization

on page 12-1

Configuration via Protocol (CvP)

on page 14-1

PCI Express Base Specification 2.1 or 3.0

Base Address Register (BAR) and Expansion ROM Settings

The type and size of BARs available depend on port type.

UG-01127_avst

2014.08.18

Base Address Register (BAR) and Expansion ROM Settings

4-5

Parameter Settings

Altera Corporation

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