Reset and clocks – Altera Arria V GZ Avalon-ST User Manual
Page 138
Reset and Clocks
7
2014.12.15
UG-01127_avst
Arria V GZ Hard IP for PCI Express IP Core includes both a soft reset controller and a hard reset
controller. Software selects the appropriate reset controller depending on the configuration you specify.
Both reset controllers reset the IP core and provide sample reset logic in the example design. The figure
below provides a simplified view of the logic that implements both reset controllers.
Table 7-1: Use of Hard and Soft Reset Controllers
Reset Controller Used
Description
Hard Reset Controller
pin_perst
from the input pin of the FPGA resets the Hard IP for PCI Express
IP Core.
app_rstn
which resets the Application Layer logic is derived from
reset_status
and
pld_clk_inuse
, which are outputs of the core. This reset
controller is supported for Gen 1 production devices.
Soft Reset Controller
Either
pin_perst
from the input pin of the FPGA or
npor
which is derived
from
pin_perst
or
local_rstn
can reset the Hard IP for PCI Express IP
Core. Application Layer logic generates the optional
local_rstn
signal.
app_
rstn
which resets the Application Layer logic is derived from
npor
.
This reset controller is supported for Gen2 and Gen3 production devices.
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