Altera Arria V GZ Avalon-ST - Manual (Page 171)

• Real-time error signals are routed to the Application Layer using the error status output signals listed
in the “Configuration Space Bypass Mode Output Signals” on page 8–44.
• Two sideband signals
uncorr_err_reg_sts
and
corr_err_reg_sts
indicate that an error has been
logged in the
Uncorrectable Error Status
or
Correctable Error Status Register
. The Applica‐
tion Layer can read these
Uncorrectable
or
Correctable Error Status Registers
,
AER Header
Log
, and
First Error Pointers
using the LMI bus to retrieve information. The
uncorr_err_reg_sts
and
corr_err_reg_sts
signals remain asserted until the Application Layer
clears the corresponding status register. Proper logging requires that the Application Layer set the
appropriate Configuration Space registers in the Transaction Layer using the LMI bus. The Applica‐
tion Layer must set the
Uncorrectable
and
Correctable Error Mask
and
Uncorrec table Error
Severity
error reporting bits appropriately so that the errors are logged appropriately internal to the
Arria V GZ Hard IP for PCI Express. The settings of the
Uncorrectable
and
Correctable Error
Mask
, and
Uncorrectable Error Severity
error reporting bits do not affect the real-time error
output signals. The Application Layer must also log these errors in the soft Configuration Space and
send error Messages.
• For more information about error handling, refer to the PCI Express Base Specification, Revision 2.0 or
3.0.
• The sideband signal
root_err_reg_sts
indicates that an error is logged in the
Root Error Status
Register
. The Application Layer can read the
Root Error Status Register
and the
Error Source
Identification Register
using the LMI bus to retrieve information about the errors. The
root_err_reg_sts
signal remains asserted until the Application Layer clears the corresponding
status register using the LMI bus. The Application Layer must set the
Uncorrectable
and
Correct-
able Error Mask
,
Uncorrectable Error Severity
, and
Device Control Register
error reporting
bits appropriately so that the errors are logged appropriately in the Arria V GZ Hard IP for PCI
Express IP Core. The settings of the
Uncorrectable
and
Correctable Error Mask
,
Uncorrectable
Error Severity
, and
Device Control Register
error reporting bits do not affect the real-time error
output signals. The Application Layer must also log these errors in the soft Configuration Space and
send error Messages.
Related Information
PCI Express Base Specification 2.1 or 3.0
UG-01127_avst
2014.08.18
Error Checking and Handling in Configuration Space Bypass Mode 10-11
IP Core Architecture Altera Corporation
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