Altera SDI II MegaCore User Manual
Page 83
Signal
Width Direction
Description
tx_rst
1
Input
Reset signal for the transmitter. This signal is active high and
level sensitive. This reset signal must be synchronous to
tx_
coreclk
clock domain.
tx_pclk
1
Input
Parallel clock input signal for the transmitter. Driven by the
tx_
clkout
signal.
• SD-SDI = 148.5 MHz
• HD-SDI = 74.25 MHz or 74.175 MHz
• 3G-SDI = 148.5 MHz or 148.35 MHz
• HD-SDI Dual Link = 74.25 MHz or 74.175 MHz
• Dual Standard = 148.5 MHz or 148.35 MHz
• Triple Standard = 148.5 MHz or 148.35 MHz
tx_datain
20
Input
User-supplied parallel data signal for the transmitter.
• SD-SDI = bits 19:10 unused; bits 9:0 C, Y, C, Y multiplex
• HD-SDI = bits 19:10 Y; bits 9:0 C
• HD-SDI dual link = bits 19:10 Y link A, bits 9:0 C link A
• 3G-SDI Level A = bits 19:10 Y; bits 9:0 C
• 3G-SDI Level B = bits 19:10 C, Y multiplex (link A); bits 9:0
C, Y multiplex (link B)
• Dual Standard = bits 19:10 Y; bits 9:0 C
• Triple Standard = bits 19:10 Y; bits 9:0 C.
Note: Not applicable for Arria 10 devices.
tx_datain_valid
1
Input
Parallel data valid signal for the transmitter. The timing (H:
High, L: Low) must be synchronous to
tx_pclk
clock domain
and have the following settings:
• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H
• 3G-SDI = H
• HD-SDI Dual Link = H
• Dual standard = SD (1H 4L 1H 5L); HD (1H 1L)
• Triple standard = SD (1H 4L 1H 5L); HD (1H 1L); 3G (H)
Otherwise, this signal can be driven by
tx_dataout_valid
for
SD-SDI, dual standard, and triple standard.
Note: Not applicable for Arria 10 devices.
rx_rst_proto_out
1
Output
Reset the receiver protocol downstream logic. This generated
signal is synchronous to
rx_clkout
clock domain and must be
used to drive the
rx_rst_proto_in
signal of the receiver
protocol block.
UG-01125
2015.05.04
SDI II IP Core Signals
4-41
SDI II IP Core Functional Description
Altera Corporation