Altera SDI II MegaCore - Manual (Page 67)

This submodule implements a pixel counter and a line counter. These counters are driven from the pixel
clock and synchronous pulses. The basic approach is to measure a synchronous pulse over time and detect
if it is consistent over a number of lines or frames. In this manner, the core can track whether the
incoming SDI is stable and locked.
The word counter monitors the EAV and SAV positions in the incoming video. This is done by
incrementing a counter on each valid word and storing the count value when an EAV or SAV is seen. If
the count values are the same as a predefined value, the incoming video is determined to be TRS locked.
The predefined value is set to 6, therefore after six consecutive lines of the same EAV and SAV timing, the
rx_trs_locked
signal is active. An enhancement allows a predefined value of consecutive missed EAV or
SAV to be tolerated without deasserting the
rx_trs_locked
signal. For example, if the predefined value is
4, this means four consecutive missed EAVs does not deassert the
rx_trs_locked
signal but five consecu‐
tive missed EAVs will deassert the signal.
The line counter increments at the start of each video line. When the first active line of a field or frame is
found, the line counter starts incrementing until the last active line of the same field or frame.
To determine the video format, a comparison logic compares the word and line count values in the video
stream against the known values predefined for various video formats. The search is done sequentially
from one known value to another.
• If the logic finds a match, the core is determined to be frame locked and the
rx_frame_locked
signal is
active. The core reports the matched known value as
rx_format
.
• If the logic does not find any match and the count is consistent over two video frames, the
rx_frame_locked
signal will still be active but the
rx_format
will stay asserted.
These values are used to compare with the word and line counts found in the subsequent video fields or
frames. The core allows a predefined value of consecutive mismatch fields or frames to be tolerated
without the
rx_frame_locked
signal. For example, if the predefined value is 4, this means four consecu‐
tive mismatch fields or frames does not deassert the
rx_frame_locked
signal but five consecutive
mismatch fields or frames will deassert the signal.
Sync Streams
This submodule is required in the HD-SDI dual link receiver as it synchronizes and deskews both data
streams received by two separate transceivers of link A and link B.
This submodule contains two FIFO buffers, where each buffer holds and transfers received data and
miscellaneous signals like line number and CRC error for each link. The read operation on both FIFO
buffers begin when the control state machine detects that both links are alignment locked
(
rx_align_locked
is active). If a TRS is first seen on link A but not link B, the control state machine halts
reading from FIFO buffer link A until TRS is seen on link B. This is also similar to the case when a TRS is
first seen on link B but not link A. Then, the core is considered locked and
rx_dl_locked
signal is active.
The SMPTE 372 specification defines that the timing difference between link A and link B must not
exceed 40 ns.
When the core is locked, the control state machine continuously sees TRS from both FIFO buffers at the
same time. If not, both links might have unaligned but it does not necessarily become TRS or frame
unlocked. The control state machine aligns both links at the next TRS without deasserting the
rx_dl_locked
signal. The control state machine only deasserts the
rx_dl_locked
signal when the
rx_trs_locked
signal is deasserted.
UG-01125
2015.05.04
Sync Streams 4-25
SDI II IP Core Functional Description Altera Corporation
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