Altera SDI II MegaCore User Manual
Page 49
• HD-SDI LN extraction
• HD-SDI CRC
• Payload ID extraction
• Synchronizing data streams
• Accessing transceiver
• Identifying and tracking of ancillary data
• Sync bit removal
The block diagrams below illustrate the SDI II IP core receiver (simplex) data path for each supported
video standard.
Figure 4-9: SD-SDI Receiver Data Path Block Diagram
Detect
Format
TRS
Aligner
Descrambler
RX
Oversample
Transceiver
Control
State Machine
Receive
Prealign
RX Protocol
RX PHY Management
& PHY Adapter
Transceiver
Parallel
Video Out
10
10
Match
TRS
10
Extract
Payload ID
10
20
SDI In
Figure 4-10: HD-SDI Receiver Data Path Block Diagram
Detect
1 & 1/1,001
Rate
Transceiver
Control
State
Machine
RX PHY
Management
& PHY Adapter Transceiver
Parallel
Video Out 20
TRS
Aligner
Descrambler
20
20
Detect
Format
Receive
RX Protocol
Match
TRS
10
Extract
Line
Check
CRC
Extract
Payload
ID
Check
CRC
Demultiplexer
Multiplexer
Y
C
10
20
SDI In
Prealign
UG-01125
2015.05.04
Receiver
4-7
SDI II IP Core Functional Description
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)