Design example components – Altera SDI II MegaCore User Manual
Page 29
Figure 3-4: Design Example Entity and Simulation Testbench for 3G-SDI (Level B) to HD-SDI Dual Link
Conversion
The figure below illustrates the generated design example entity and simulation testbench when you
generate 3G-SDI or triple rate SDI receiver with Convert 3G-SDI (level B) to HD-SDI dual link option
enabled.
Loopback
Path
Ch0
Loopback
(SDI Duplex)
Reconfiguration
Management/Router
Ch1 Test
(3-Gb SDI TX)
Ch1 DUT
(3-Gb SDI RX)
B to A
Video Pattern
Generator
Test
Control
Ch2 Test
(HD DL SDI TX)
Ch2 Test
(HD DL SDI RX)
TX
Checker
RX
Checker
Loopback
Path
Data
Control
SDI II IP Core
Design Example
Testbench
Transceiver
Reconfiguration
Controller
Design Example Components
The Arria V, Cyclone V, and Stratix V design examples for the SDI II IP core consist of the following
components:
• Video pattern generator
• Transceiver reconfiguration controller
• Reconfiguration management
• Reconfiguration router
3-14
Design Example Components
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Getting Started
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)