Reconfiguration management – Altera SDI II MegaCore User Manual
Page 31
Transceiver Reconfiguration Controller for Arria V, Cyclone V, and Stratix V
For Arria V, Cyclone V, and Stratix V design examples, the transceiver reconfiguration controller allows
you to change the device transceiver settings at any time. Any portion of the transceiver can be selectively
reconfigured. Each portion of the reconfiguration requires a read-modify-write operation (read first, then
write), in such a way by modifying only the appropriate bits in a register and not changing other bits.
Prior to this operation, you must define the logical channel number and the streamer module mode.
You can perform a transceiver dynamic reconfiguration in these two modes:
• streamer module mode 1 (manual mode)—execute a series of Avalon
®
Memory-Mapped (Avalon-
MM) write operation to change the transceiver settings. In this mode, you can execute a write
operation directly from the reconfiguration management/router interface to the device transceiver
registers.
• streamer module mode 0—use the .mif files to change the transceiver settings.
For read operation, after defining the logical channel number and the streamer module mode, the
following sequence of events occur:
1. Define the transceiver register offset in the offset register.
2. Read the data register. Toggle the read process by setting bit 1 of the control and status register (CSR)
to logic 1.
3. Once the busy bit in the CSR is cleared to logic 0, it indicates that the read operation is complete and
the required data should be available for reading.
For write operation, after setting the logical channel number and the streamer module mode, the
following sequence of events occur:
1. Define the transceiver register offset (in which the data will be written to) in the offset register.
2. Write the data to the data register. Toggle the write process by setting bit 0 of the CSR to logic 1.
3. Once the busy bit in the CSR is cleared to logic 0, it indicates that the transceiver register offset
modification is successful.
For more information about the transceiver reconfiguration controller streamer module, refer to the
Transceiver Reconfiguration Controller IP Core Overview chapter of the Altera Transceiver PHY IP Core
User Guide.
Related Information
More information about the transceiver reconfiguration controller streamer module.
Reconfiguration Management
The reconfiguration management block (
sdi_ii_ed_reconfig_mgmt.v
and
sdi_ii_reconfig_logic.v
) contains the
reconfiguration user logic (a finite state machine) to determine the bits that needs to be modified, and
selects the correct data to be written to the appropriate transceiver register through streamer module
mode 1. It also provides handshaking between the SDI receiver and the transceiver reconfiguration
controller. In this design, each reconfiguration block must interface with only one transceiver reconfigu‐
ration controller.
During the reconfiguration process, the logic first reads the data from the transceiver register that needs
to be reconfigured and stores the data temporarily in a local register. Then, the logic overwrites only the
appropriate bits of the data with predefined values and write the modified data to the transceiver register.
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Transceiver Reconfiguration Controller for Arria V, Cyclone V, and...
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Getting Started