Altera SDI II MegaCore User Manual
Page 50

Figure 4-11: 3G-SDI Receiver Data Path Block Diagram
Detect
Format
TRS
Aligner
Descrambler
Detect
1 & 1/1,001
Rate
Transceiver
Control
State
Machine
Receive
Prealign
RX Protocol
RX PHY
Management
& PHY Adapter Transceiver
Parallel
Video Out 20
20
Match
TRS
10
Extract
Line
20
Check
CRC
Extract
Payload
ID
Check
CRC
3Gb Demultiplexer
Multiplexer
Y
C
10
Match
TRS
10
Extract
Line
Check
CRC
Extract
Payload
ID
Check
CRC
10
Y Link B
(3 Gb)
C Link B
(3 Gb)
Y or
Y Link A
(3 Gb)
C or
C Link A
(3 Gb)
20
SDI In
Figure 4-12: Dual Rate SDI Receiver Data Path Block Diagram
Detect
Format
TRS
Aligner
Descrambler
Detect
Video
Standard
Transceiver
Control
State
Machine
Receive
Prealign
RX Protocol
RX PHY
Management
& PHY Adapter
Transceiver
Parallel
Video Out 20
20
Match
TRS
10
Extract
Line
20
Check
CRC
Extract
Payload
ID
Check
CRC
Demultiplexer
Multiplexer
Y (HD)
C (HD)
or CY (SD)
10
RX
Oversample
20
20
SDI In
Detect
1 & 1/1,001
Rate
4-8
Receiver
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)