Descrambler, Descrambler -22 – Altera SDI II MegaCore User Manual
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The transceiver controller uses a different approach to detect the incoming video standard. Instead of
setting the core to each of the standards and waiting to see if lock is achieved, the core directly analyzes
the incoming stream and try to determine the rate. This is done by looking at the edge density, or by
number of transitions in the incoming stream as described in the Detect Video Standard section.
The core is set into the highest data rate mode (transceiver running at 2.97 Gbps for 3G-SDI and 11.88
Gbps for 12G-SDI) and in lock-to-refclk (LTR) mode. It is essentially running in a fixed frequency
sampling mode. The core examines for transitions in the data stream. The number of transitions in the
incoming stream is counted over a fixed period of time.
Compare the edge count value with a number of fixed values that correspond to the thresholds of the
video standards. This approach works because the scrambling algorithm in the SDI guarantees a
maximum and a minimum number of transitions in the SDI stream.
The output of this circuit determines if the transceiver requires dynamic reconfiguration to a new mode.
The dual and triple rate SDI core uses 11x oversampling for the reception of SD-SDI. This means that you
require only two transceiver setups since the rates for 3G-SDI and 11x SD-SDI are the same. For multi
rate (up to 12G) modes, you require two more setups to accomodate 6G-SDI and 12G-SDI.
The transceiver controller uses the presence (or absence) of TRSs on the stream to determine if the SDI
signal is correctly received. The detect format submodule indicates to the transceiver controller that the
receiver is acquiring some valid SDI samples when it detects a single and valid TRS. The transceiver
controller only deasserts this flag when it does not detect any EAV sequences within the number of
consecutive lines specified. At this point, the transceiver controller state machine resets and performs the
relock algorithm.
The receive transceivers can be set into one of two modes, manual or automatic. In automatic mode, a
state machine internal to the transceiver controls the training. In manual mode, the external logic must
take care of the transceiver training by using either lock-to-refclk (LTR) or lock-to-data (LTD) mode.
• In LTR mode, a state machine internal to the receive transceiver uses the applied reference clock for
operation. The core samples the incoming data using the
refclk
signal and does not perform clock
recovery. The sampling clock does not lock to the incoming data stream. Use this mode for transceiver
training and in the oversampling modes of SD-SDI. In this mode, the
rx_clkout
signal of the
transceiver is a mirror of the reference clock.
• In LTD mode, a state machine internal to the receive transceiver uses the clock generated by the CDR
circuitry. The CDR extracts a clock from the incoming data stream and uses the clock to sample the
incoming data. The sampling clock locks to the incoming data. You can only use this mode after the
transceiver has been trained. Use this mode to recover data for HD and 3G streams. In this mode, the
rx_clkout
signal of the transceiver locks to the data.
Related Information
The detect video standard submodule performs coarse rate detection on the incoming video stream for
dual, triple, or multi rate SDI.
Descrambler
This submodule implements data descrambling as defined in the SMPTE259 and SMPTE292 specifica‐
tions. This submodule is similar to the scrambler submodule, where it implements the reverse of the
scrambling applied to the data. This submodule uses an LFSR and also implements NRZI.
4-22
Descrambler
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description