Altera SDI II MegaCore - Manual (Page 63)

Detect Video Standard
The detect video standard submodule performs coarse rate detection on the incoming video stream for
dual, triple, or multi rate SDI.
This scheme is required so the SDI II IP core can reprogram the transceivers to the correct settings for the
video standard present at the input.
The submodule executes the detection process in the following manner:
1. Look for transitions in the incoming data words by comparing each bit with the adjacent bit in the
incoming word. Then, generate a bus with one bit set for each transition or edge seen.
2. Count the number of bit sets in the bus and return a value, which represents the number of edges
present in a particular input data word.
3. Count the total number of edges seen over a given number of input words using an accumulator.
Then, add the number of transitions seen in the current input word to a running total of transitions
seen since the accumulator was reset.
4. Compare the total number of edges with a fixed set of values determined by experimentation. The
actual thresholds are relative to the data rates of the three standards.
This submodule asserts the
rate_detect_done
flag to indicate to the transceiver controller submodule
that rate detection has been performed. This approach is further described in the Transceiver Controller
section.
Related Information
Transceiver Controller on page 4-21
The transceiver controller controls the transceiver to achieve the desired receiver functionality for the
SDI.
Detect 1 and 1/1.001 Rates
This submodule indicates if the incoming video stream is running at PAL (1) or NTSC (1/1.001) rate. The
output port signal,
rx_clkout_is_ntsc_paln
is set to 0 if the submodule detects the incoming stream as
PAL (148.5 MHz or 74.25 MHz recovered clock) and set to 1 if the incoming stream is detected as NTSC
(148.35 MHz or 74.175 MHz recovered clock).
For correct video rate detection, you must set the top level port signal,
rx_coreclk_is_ntsc_paln
, to the
following bit:
• 0 if the
rx_coreclk
signal is 148.5 MHz or 74.25 MHz
• 1 if the
rx_coreclk
signal is 148.35 MHz or 74.175 MHz
Transceiver Controller
The transceiver controller controls the transceiver to achieve the desired receiver functionality for the
SDI.
When the interface receives SD-SDI, the transceiver receiver PLL locks to the receiver reference clock.
When the interface receives HD-SDI, the transceiver receiver PLL is first trained by locking to the receiver
reference clock. When the PLL is locked, it can then track the actual receiver data rate. If a period of time
passes without a valid SDI signal, the PLL is retrained with the reference clock and the process repeats.
UG-01125
2015.05.04
Detect Video Standard 4-21
SDI II IP Core Functional Description Altera Corporation
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