Sdi ii ip core functional description, Sdi ii ip core functional description -1 – Altera SDI II MegaCore User Manual
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SDI II IP Core Functional Description
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2015.05.04
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The SDI II IP core implements a transmitter, receiver, or full-duplex interface.
The SDI II IP core consists of the following components:
• Protocol block—transmitter or receiver
• Transceiver blocks—PHY management & adapter and hard transceiver
In the parameter editor, you can specify either protocol, transceiver, or combined blocks for your design.
For example, if you have multiple protocol blocks in a design, you can multiplex them into one
transceiver.
The modular hierarchy design allows you to remove or reuse each submodule within the components
across different video standards. The transmitter and receiver data paths are independent from each
other.
The following figure shows the block diagram for non-Arria 10 devices.
Figure 4-1: SDI II IP Core Block Diagram for Arria V, Cyclone V, and Stratix V Devices
Transceiver
SDI II IP Core
Parallel Video In
Parallel Video Out
SDI Out
SDI In
20
20
20
20
Protocol
PHY Management
& PHY Adapter
Hard Transceiver
For the Arria 10 devices, the SDI II IP core no longer provides the transceiver, and the TX PLL is no
longer wrapped in the transceiver PHY. You must generate the transceiver and the TX PLL separately.
The figure below shows the block diagram for Arria 10 devices.
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