Testbench example design – Altera SDI II MegaCore User Manual
Page 25
Figure 3-1: Design Example Entity and Simulation Testbench for Arria 10 Devices
Loopback
Path
Ch0 Loopback
(SDI TX + RX)
Arria 10 Native
PHY (Duplex)
Ch0 RX
Transceiver
Reset Controller
Pattern
Generator
Ch1 DUT
(SDI TX)
Arria 10 Native
PHY (TX)
Ch1 RX
Transceiver
Reset Controller
Ch0 TX
Transceiver
Reset Controller
Ch1 TX
Transceiver
Reconfiguration
Controller
Ch0 TX
PLL
Ch1 Test
(SDI RX)
Arria 10 Native
PHY (RX)
Ch0 TX
Transceiver
Reset Controller
Ch0 Duplex
Transceiver
Reconfiguration
Controller
Ch0 TX
PLL
Ch1 RX
Transceiver
Reconfiguration
Controller
TX Checker
RX
Checker
Test
Control
Testbench
Example Design
Data
Control
SDI II IP Core
Arria 10 Native PHY IP Core
Transceiver PHY Reset Controller IP Core
Arria 10 Transceiver CMU/ATX PLL IP Core
3-10
Design Examples for Arria 10 Devices
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Getting Started
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)