Altera SDI II MegaCore User Manual
Page 40
Signal
Width
Direction
Description
pll_sel
1
Input
Signal to specify which TX PLL to use. This
signal must share the same source as
pll_
select
signal in the transceiver PHY reset
controller.
pll_sw_req
1
Input
Request signal to start the PLL switching
dynamic reconfiguration.
Note: Do not assert this signal when
other reconfiguration signals are
busy, for example
cdr_reconfig_
busy
.
pll_busy
1
Output
Status signal that indicates that the PLL
switching process is taking place.
external_avmm_master_req
1
Input
Request signal from the external Avalon-MM
master. Tie this signal to 0 if you do not use
the external Avalon-MM master.
reconfig_write_from_ext_
avmm_master
1
Input
Write enable signal. Connect this signal to the
write signal of the external Avalon-MM
master if you have one in your design.
reconfig_read_from_ext_
avmm_master
1
Input
Read enable signal. Connect this signal to the
read signal of the external Avalon-MM
master if you have one in your design.
reconfig_address_from_ext_
avmm_master
10
Input
Reconfiguration address. Connect this signal
to the
reconfig address
bus of the external
Avalon-MM master if you have one in your
design.
reconfig_writedata_from_
ext_avmm_master
32
Input
A 32-bit data write bus. Connect this bus to
the
reconfig data write
bus of the
external Avalon-MM master if you have one
in your design.
reconfig_readdata_from_ext_
avmm_master
32
Output
A 32-bit data read bus. Connect this bus to
the
reconfig data read
bus of the external
Avalon-MM master if you have one in your
design.
reconfig_waitrequest_from_
ext_avmm_master
1
Output
Status signal that indicates that the Avalon-
MM is busy. Connect this signal to the
waitrequest
signal of the external Avalon-
MM master if you have one in your design.
Note: Do not issue any Avalon
commands when this signal is
high.
UG-01125
2015.05.04
Transceiver Reconfiguration Controller Signals
3-25
SDI II IP Core Getting Started
Altera Corporation