Altera Integer Arithmetic IP - Manual (Page 85)

Verilog HDL Prototype
To view the Verilog HDL prototype for the megafunction, refer to the Verilog Design File (.v) altera_mf.v
in the \eda\synthesis directory.
VHDL Component Declaration
To view the VHDL component declaration for the megafunction, refer to the VHDL Design File (.vhd)
altera_mf_components.vhd in the
\libraries\vhdl\altera_mf directory.
VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ALTMULT_ACCUM Ports
The following tables list the input and output ports for the ALTMULT_ACCUM megafunction.
Note: For Arria V, Cyclone V, and Stratix V devices, each register can select between two asynchronous
clear signals (
ACLR0
,
ACLR1
) and three clock/enable pairs (
CLOCK0
/
ENA0
,
CLOCK1/ENA1
,
CLOCK2/
ENA2
).
Table 8-2: ALTMULT_ACCUM Megafunction Input Ports
Port Name Required Description
accum_sload
No
Causes the value on the accumulator feedback path to go to
zero (0) or to
accum_sload_upper_data
when concatenated
with 0. If the accumulator is adding and the
accum_sload
port
is high, then the multiplier output is loaded into the
accumulator. If the accumulator is subtracting, then the
opposite (negative value) of the multiplier output is loaded
into the accumulator.
Beginning from Stratix V devices onwards, the
accum_sload
port causes the value on the accumulator feedback path to go
to zero (0) or to
accum_sload_upper_data
when concaten‐
ated with 1 and loads the multiplier output if the accum_sload
port is low.
aclr0
No The first asynchronous clear input. The
aclr0
port is active
high.
aclr1
No The second asynchronous clear input. The
aclr1
port is
active high.
8-4 Verilog HDL Prototype
UG-01063
2014.12.19
Altera Corporation ALTMULT_ACCUM (Multiply-Accumulate)
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