Altera Integer Arithmetic IP - Manual (Page 21)

output cout;
output [15:0] eq;
input cin;
input [lpm_width-1:0] data;
input clock, clk_en, cnt_en, updown;
input aset, aclr, aload;
input sset, sclr, sload;
endmodule
VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd) LPM_PACK.vhd in the
\libraries\vhdl\lpm directory.
component LPM_MULT
generic ( LPM_WIDTHA : natural;
LPM_WIDTHB : natural;
LPM_WIDTHS : natural := 1;
LPM_WIDTHP : natural;
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : natural := 0;
LPM_TYPE: string := L_MULT;
LPM_HINT : string := "UNUSED");
port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
VHDL LIBRARY_USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY lpm;
USE lpm.lpm_components.all;
Ports
The following tables list the input and output ports for the LPM_COUNTER megafunction.
Table 2-2: LPM_COUNTER Megafunction Input Ports
Port Name Required Description
data[]
No Parallel data input to the counter. The size of the input port
depends on the
LPM_WIDTH
parameter value.
clock
Yes Positive-edge-triggered clock input.
clk_en
No Clock enable input to enable all synchronous activities. If omitted,
the default value is
1
.
UG-01063
2014.12.19
VHDL Component Declaration 2-3
LPM_COUNTER (Counter) Altera Corporation
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