Verilog hdl prototype, Vhdl component declaration, Verilog hdl prototype -2 – Altera Integer Arithmetic IP User Manual
Page 148: Vhdl component declaration -2
Device family
Input data
width
Output
latency
Logic Usage
f
MAX
(MHz)
(8)
Adaptive
Look-Up
Table (ALUT)
Dedicated
Logic
Register
(DLR)
Adaptive
Logic
Module
(ALM)
Stratix III
8
1
28
0
14
547
20
5
131
0
90
321
30
3
256
0
152
71
Stratix IV
8
1
28
0
14
350
20
5
131
0
94
267
30
3
256
0
154
66
Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v) altera_mf.v in the
module altsqrt
# (parameter lpm_hint = "UNUSED",
parameter lpm_type = "altsqrt",
parameter pipeline = 0,
parameter q_port_width = 1,
parameter r_port_width = 1,
parameter width = 1)
(input wire aclr,
input wire clk,
input wire ena,
output wire [q_port_width-1:0] q,
input wire [width-1:0] radical,
output wire [r_port_width-1:0] remainder);
endmodule
VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd)
altera_mf_components.vhd in the
\libraries\vhdl\altera_mf
directory.
component altsqrt
generic (
lpm_hint:string := "UNUSED";
lpm_type:string := "altsqrt";
pipeline:natural := 0;
q_port_width:natural := 1;
r_port_width:natural := 1;
width:natural);
port(
aclr:in std_logic := '0';
(8)
The performance of the megafunction is dependant on the value of the maximum allowable ceiling f
MAX
that the selected device can achieve. Therefore, results may vary from the numbers stated in this column.
11-2
Verilog HDL Prototype
UG-01063
2014.12.19
Altera Corporation
ALTSQRT (Integer Square Root)