Altera Integer Arithmetic IP - Manual (Page 13)

Figure 1-6: IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
.qip - Lists files for synthesis
testbench - Simulation testbench files
1
- Testbench for supported simulators
.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
.sip - NativeLink simulation integration file
- Simulator setup scripts
- IP core variation files
.qip or .qsys - System or IP integration file
_generation.rpt - IP generation report
.bsf - Block symbol schematic file
.ppf - XML I/O pin information file
.spd - Combines individual simulation startup scripts
1
.html - Contains memory map
.sopcinfo - Software tool-chain integration file
_syn.v or .vhd - Timing & resource estimation netlist 1
.debuginfo - Lists files for synthesis
.v, .vhd, .vo, .vho - HDL or IPFS models
2
_tb - Testbench for supported simulators
_tb.v or .vhd - Top-level HDL testbench file
Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading
before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to
identify and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
1-8 Upgrading IP Cores
UG-01063
2014.12.19
Altera Corporation Integer Arithmetic Megafunctions
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