Altera Integer Arithmetic IP - Manual (Page 4)

Verilog HDL Prototype...............................................................................................................................8-4
VHDL Component Declaration................................................................................................................ 8-4
VHDL LIBRARY_USE Declaration..........................................................................................................8-4
ALTMULT_ACCUM Ports........................................................................................................................8-4
ALTMULT_ACCUM Parameters.............................................................................................................8-6
Design Example: Shift Accumulator....................................................................................................... 8-19
Understanding the Simulation Results................................................................................................... 8-19
ALTMULT_ADD (Multiply-Adder)...................................................................9-1
Features......................................................................................................................................................... 9-3
Pre-adder...........................................................................................................................................9-4
Systolic Delay Register.....................................................................................................................9-7
Pre-load Constant..........................................................................................................................9-10
Double Accumulator.....................................................................................................................9-10
Resource Utilization and Performance...................................................................................................9-11
Verilog HDL Prototype.............................................................................................................................9-11
VHDL Component Declaration.............................................................................................................. 9-11
VHDL LIBRARY_USE Declaration........................................................................................................9-12
ALTMULT_ADD Ports............................................................................................................................9-12
ALTMULT_ADD Parameters................................................................................................................. 9-14
Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter............................. 9-34
Understanding the Simulation Results................................................................................................... 9-35
ALTMULT_COMPLEX (Complex Multiplier)................................................ 10-1
Complex Multiplication............................................................................................................................10-2
Canonical Representation.........................................................................................................................10-2
Conventional Representation...................................................................................................................10-3
Features....................................................................................................................................................... 10-3
Resource Utilization and Performance...................................................................................................10-4
Verilog HDL Prototype.............................................................................................................................10-4
VHDL Component Declaration.............................................................................................................. 10-5
VHDL LIBRARY_USE Declaration........................................................................................................10-5
ALTMULT_COMPLEX Ports................................................................................................................. 10-6
ALTMULT_COMPLEX Parameters.......................................................................................................10-6
Design Example: Multiplication of 8-bit Complex Numbers Using Canonical Representation...
10-8
Understanding the Simulation Results................................................................................................... 10-8
ALTSQRT (Integer Square Root)..................................................................... 11-1
Features....................................................................................................................................................... 11-1
Resource Utilization and Performance...................................................................................................11-1
Verilog HDL Prototype.............................................................................................................................11-2
VHDL Component Declaration.............................................................................................................. 11-2
VHDL LIBRARY_USE Declaration........................................................................................................11-3
Ports.............................................................................................................................................................11-3
Parameters.................................................................................................................................................. 11-3
TOC-4 Integer Arithmetic IP Cores User Guide
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