Altera Integer Arithmetic IP - Manual (Page 2)

Contents
Integer Arithmetic Megafunctions..................................................................... 1-1
Design Example Files...................................................................................................................................1-2
Installing and Licensing IP Cores..............................................................................................................1-2
Customizing and Generating IP Cores.....................................................................................................1-2
IP Catalog and Parameter Editor...............................................................................................................1-3
Using the Parameter Editor........................................................................................................................1-4
Specifying IP Core Parameters and Options............................................................................................1-4
Specifying IP Core Parameters and Options (Legacy Parameter Editors)...........................................1-6
Files Generated for Altera IP Cores (Legacy Parameter Editor)............................................... 1-7
Upgrading IP Cores.....................................................................................................................................1-8
Migrating IP Cores to a Different Device...............................................................................................1-11
Simulating Altera IP Cores in other EDA Tools................................................................................... 1-12
LPM_COUNTER (Counter)................................................................................2-1
Features......................................................................................................................................................... 2-1
Resource Utilization and Performance.....................................................................................................2-2
Verilog HDL Prototype...............................................................................................................................2-2
VHDL Component Declaration................................................................................................................ 2-3
VHDL LIBRARY_USE Declaration..........................................................................................................2-3
Ports...............................................................................................................................................................2-3
Parameters.....................................................................................................................................................2-5
LPM_DIVIDE (Divider)......................................................................................3-1
Features......................................................................................................................................................... 3-1
Resource Utilization and Performance.....................................................................................................3-1
Verilog HDL Prototype...............................................................................................................................3-2
VHDL Component Declaration................................................................................................................ 3-2
VHDL LIBRARY_USE Declaration..........................................................................................................3-3
Ports...............................................................................................................................................................3-3
Parameters.....................................................................................................................................................3-3
LPM_MULT (Multiplier).................................................................................... 4-1
Features......................................................................................................................................................... 4-1
Resource Utilization and Performance.....................................................................................................4-1
Verilog HDL Prototype...............................................................................................................................4-2
VHDL Component Declaration................................................................................................................ 4-3
VHDL LIBRARY_USE Declaration..........................................................................................................4-3
LPM_MULT Ports.......................................................................................................................................4-3
LPM_MULT Parameters............................................................................................................................ 4-4
TOC-2 Integer Arithmetic IP Cores User Guide
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