Altera MAX 10 FPGA - Manual (Page 55)

Document Revision History for MAX 10 FPGA Configuration User Guide
Date Version Changes
May 2015 2015.05.04 • Rearranged and updated Configuration Setting names 'Initializa‐
tion Configuration Bits for MAX 10 Devices' table.
• Updated 'High-Level Overview of Internal Configuration for MAX
10 Devices' figure with JTAG configuration and moved the figure
to 'Configuration Schemes' section.
• Added link to corresponding description of configuration settings
in 'Initialization Configuration Bits for MAX 10 Devices' table.
• Updated the default watchdog time value from hexadecimal to
decimal value in 'Initialization Configuration Bits for MAX 10
Devices' table.
• Updated the ISP data description in 'Initialization Configuration
Bits for MAX 10 Devices' table.
• Updated 'User Watchdog Timer' by adding time-out formula.
• Added link to 'User Watchdog Internal Circuitry Timing Specifica‐
tions' in MAX 10 FPGA Device Datasheet.
• Added footnote to indicate that JTAG secure is disabled by default
and require Altera support to enable in 'Initialization Configura‐
tion Bits for MAX 10 Devices' table.
• Updated minimum and maximum CRC calculation time for
divisor 2.
• Updated remote system upgrade flow diagram.
• Updated 'Encryption in Internal Configuration' table by adding
'Key' terms and changed Image 1 and Image 2 to Image 0 and
Image 1 respectively.
• Added footnote to 'Encryption in Internal Configuration' to
indicate auto-reconfiguration when image fails.
• Added formula to calculate minimum and maximum CRC calcula‐
tion time for other than divisor 2.
• Added caution when JTAG Secure is turned on.
• Added information about auto-generated .pof for certain type of
internal configuration modes.
• Added .pof and ICB setting guide through Device and Pin Options
and convert programming file.
• Added configuration RAM (CRAM) in 'Overview'
• Editorial changes.
A-2 Document Revision History for MAX 10 FPGA Configuration User Guide
UG-M10CONFIG
2015.05.04
Altera Corporation Additional Information for MAX 10 FPGA Configuration User Guide
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