Altera MAX 10 FPGA - Manual (Page 11)

Instruction Instruction Code Description
BGP_ENABLE 01 1001 1001 • Sets the device to the real-time ISP mode.
• Allows access to the internal flash configuration
sector while the device is still in user mode.
BGP_DISABLE 01 0110 0110 • Brings the device out of the real-time ISP mode.
• The device has to exit the real-time ISP mode using
the
BGP_DISABLE
instruction after it is interrupted by
reconfiguration.
Caution: Do not use unsupported JTAG instructions. It will put the device into an unknown state and
requires a power cycle to recover the operation.
Initialization Configuration Bits
Initialization Configuration Bits (ICB) stores the configuration feature settings of the MAX 10 device. You
can set the ICB settings during Convert Programming File.
Table 2-5: Initialization Configuration Bits for MAX 10 Devices
Configuration Settings Description Default State/Value
Power On Reset Scheme
• Instant ON
• Fast POR delay
• Slow POR delay
Instant ON
Set I/O to weak pull-up prior
usermode
• Enable: I/O will set to week pull-up prior to
usermode.
• Disable: I/O will be input tri-stated.
Enable
Auto-reconfigure from
secondary image when initial
image fails.
Enable:
• Device will automatically load secondary image
if initial image fails.
Disable:
• device will automatically load image 0.
• device will not load image 1 if image 0 fails.
•
CONFIG_SEL
pin setting is ignored.
Enable
Use secondary image ISP data
as default setting when
available.
• Disable: Use ISP data from image 0
• Enable: Use ISP data from image 1
ISP data contains the information about state of
the pin during ISP. This can be either tri-state with
weak pull-up or clamp the I/O state. You can set
the ISP clamp through Device and Pin Option, or
Pin Assignment tool.
Disable
Verify Protect To disable or enable the Verify Protect feature. Disable
UG-M10CONFIG
2015.05.04
Initialization Configuration Bits 2-7
MAX 10 FPGA Configuration Schemes and Features Altera Corporation
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