Altera MAX 10 FPGA - Manual (Page 3)

MAX 10 FPGA Configuration IP Core Implementation Guides...................... 4-1
Altera Unique Chip ID IP Core................................................................................................................. 4-1
Instantiating the Altera Unique Chip ID IP Core....................................................................... 4-1
Resetting the Altera Unique Chip ID IP Core............................................................................. 4-1
Altera Dual Configuration IP Core........................................................................................................... 4-1
Instantiating the Altera Dual Configuration IP Core................................................................. 4-2
Altera Dual Configuration IP Core References..................................................5-1
Altera Dual Configuration IP Core Avalon-MM Address Map............................................................5-1
Altera Dual Configuration IP Core Parameters...................................................................................... 5-3
Altera Unique Chip ID IP Core References........................................................6-1
Altera Unique Chip ID IP Core Ports.......................................................................................................6-1
Additional Information for MAX 10 FPGA Configuration User Guide..........A-1
Document Revision History for MAX 10 FPGA Configuration User Guide.....................................A-2
TOC-3
Altera Corporation