Altera MAX 10 FPGA - Manual (Page 39)

In user mode, MAX 10 devices support the
CHANGE_EDREG
JTAG instruction, which allows you to write to
the 32-bit storage register. You can use .jam to automate the testing and verification process. You can
only execute this instruction when the device is in user mode. This instruction enables you to dynamically
verify the CRC functionality in-system without having to reconfigure the device. You can then switch to
use the CRC circuit to check for real errors induced by an SEU.
After the test completes, to clear the CRC error and restore the original CRC value, power cycle the device
or follow these steps:
1. After the configuration completes, use
CHANGE_EDREG
JTAG instruction to shift out the correct
precomputed CRC value and load the wrong CRC value to the CRC storage register. When an error is
detected, the
CRC_ERROR
pin will be asserted.
2. Use
CHANGE_EDREG
JTAG instruction to shift in the correct precomputed CRC value. The
CRC_ERROR
pin is de-asserted to show that the error detection CRC circuitry is working.
Related Information
SEU Mitigation and Configuration Error Detection on page 2-18
Enabling Error Detection
The CRC error detection feature in the Quartus II software generates the
CRC_ERROR
output to the
optional dual-purpose
CRC_ERROR
pin.
To enable the error detection feature using CRC, follow these steps:
1. Open the Quartus II software and load a project using MAX 10 device family.
2. On the Assignments menu, click Settings. The Settings dialog box appears.
3. In the Category list, select Device.
4. Click Device and Pin Options.
5. In the Device and Pin Options dialog box, click the Error Detection CRC tab.
6. Turn on Enable error detection CRC.
7. In the Divide error check frequency by field, enter a valid divisor.
The divisor value divides down the frequency of the configuration oscillator output clock. This output
clock is used as the clock source for the error detection process.
8. Click OK.
Related Information
SEU Mitigation and Configuration Error Detection on page 2-18
Accessing Error Detection Block Through User Interface
The error detection circuit stores the computed 32-bit CRC signature in a 32-bit register. The user logic
from the core reads out this signature. The
fiftyfivenm_crcblock
primitive is a WYSIWYG component
used to establish the interface from the user logic to the error detection circuit. The
fiftyfivenm_crcblock
primitive atom contains the input and output ports that must be included in the
atom. To access the logic array,you must insert the
fiftyfivenm_crcblock
WYSIWYG atom into your
design. The recommended clock frequency of .clk port is to follow the clock frequency of EDCRC block.
UG-M10CONFIG
2015.05.04
Enabling Error Detection 3-9
MAX 10 FPGA Configuration Design Guidelines Altera Corporation
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