Altera MAX 10 FPGA - Manual (Page 52)

• Avalon Interface Specifications
Provides more information about the Avalon-MM interface specifications applied in Altera Dual
Configuration IP Core.
• Instantiating the Altera Dual Configuration IP Core on page 4-2
• Accessing the Remote System Upgrade Block Through User Interface on page 3-8
Altera Dual Configuration IP Core Parameters
Table 5-2: Altera Dual Configuration IP Core Parameter for MAX 10
Parameter Value Description
Clock frequency Up to 80MHz Specifies the number of cycle to assert
RU_nRSTIMER
and
RU_
nCONFIG
signals. Note that maximum
RU_CLK
is 40Mhz, Altera
Dual Configuration IP Core has restriction to run at 80Mhz
maximum, which is twice faster than hardware limitation. This is
because Altera Dual Configuration IP Core generate
RU_CLK
at
half rate of the input frequency.
UG-M10CONFIG
2015.05.04
Altera Dual Configuration IP Core Parameters 5-3
Altera Dual Configuration IP Core References Altera Corporation
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