Altera unique chip id ip core, Instantiating the altera unique chip id ip core, Resetting the altera unique chip id ip core – Altera MAX 10 FPGA User Manual
Page 48: Altera dual configuration ip core, Altera unique chip id ip core -1, Instantiating the altera unique chip id ip core -1, Resetting the altera unique chip id ip core -1, Altera dual configuration ip core -1
MAX 10 FPGA Configuration IP Core
Implementation Guides
4
2015.05.04
UG-M10CONFIG
Altera Unique Chip ID IP Core
This section provides the guideline to implement the Altera Unique Chip ID IP Core.
Related Information
•
on page 2-16
•
Altera Unique Chip ID IP Core Ports
Instantiating the Altera Unique Chip ID IP Core
To instantiate the Altera Unique Chip ID IP Core, follow these steps:
1. On the Tools menu of the Quartus II software, click IP Catalog.
2. Under the Library category, expand the Basic Functions and Configuration Programming.
3. Select Altera Unique Chip ID and click Add, and enter your desired output file name
4. In the Save IP Variation dialog box:
• Set your IP variation filename and directory.
• Select IP variation file type.
5. Click Finish.
Resetting the Altera Unique Chip ID IP Core
To reset the Altera Unique Chip ID IP core, you must assert high to the
reset
signal for at least one clock
cycle. After you de-assert the
reset
signal, the Altera Unique Chip ID IP core re-reads the unique chip ID
of your device from the fuse ID block. The Altera Unique Chip ID IP core asserts the
data_valid
signal
after completing the operation.
Altera Dual Configuration IP Core
This section provides the guideline to implement the Altera Dual Configuration IP Core.
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