Rockwell Automation 1746-HSCE,D17466.5 High-Speed Counter Module - Manual (Page 77)

Publication 1746-UM006B-EN-P - August 2005
Configuration and Programming 4-17
I:e.0 bit 3 - Rate Valid
This bit is cleared upon the 0 to 1 transition of the Function Control
bit.
The module sets this bit to 1 when the Rate Measurement and Rate
Period Count inputs have valid values that do not cause any
overflows. The bit is updated after every Rate Period.
I:e.0 bit 4 - Rate Counter Overflow
When this bit is set, a Rate Period Counter overflow has been
detected. The bit is dynamically updated after every Rate Period. You
can adjust the Rate Period when an overflow is detected. When the
overflow occurs, the Rate Period will be set to ±32767. Refer to Rate
Counter Overflow in Chapter 5.
The module sets this bit to 1 when the Rate Period Counter
Overflows. This bit is cleared upon the 0 to 1 transition of the
Function Control bit.
Rate Valid (bit 3) Condition
0 Rate Measurement and Rate Period Count inputs do
not have meaningful data
1 Rate Measurement and Rate Period Count inputs have
valid values that do not cause any overflows
Rate Counter Overflow (bit 4) Cause
0 No Rate Period overflow detected
1 Rate Period Counter overflow detected