Agilent Technologies HDMP-3001 - Manual (Page 121)

121
APPROX. 750 ns
E1, E2, F1
B1 B2 B3 B4 B5 B6 B7 B8
RX_FRAME_SFP
RX_SONETCLK
RX_E1E2F1_CLK
Figure 44. Receive Overhead Clock and Data Alignment
The receive overhead alignment timing diagram (Figure 44) shows the relationship between the
RX_E1_DATA, RX_E2_DATA and RX_F1_DATA serial data outputs and their associated clock
RX_E1E2F1_CLK. It is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate
and is aligned as shown in Figure 44.