IEI Integration NANO-945GSE v1.01 - Manual (Page 49)

NANO-945GSE EPIC Motherboard
Page 29
Keyboard Controller
Watchdog Timer
Some of the Super I/O features are described in more detail below:
2.6.3.1 Super I/O LPC Interface
The LPC interface on the Super I/O complies with the Intel
®
Low Pin Count Specification
Rev. 1.0. The LPC interface supports both LDRQ# and SERIRQ protocols as well as PCI
PME# interfaces.
2.6.3.2 Super I/O 16C550 UARTs
The onboard Super I/O has two integrated 16C550 UARTs that can support the following:
Two standard serial ports (COM1 and COM2)
IrDa 1.0 and ASKIR protocols
Another chipset connected to the LPC bus provided connectivity to another two serial port
connectors (COM3 and COM4).
2.6.3.3 Super I/O Digital Input/Output
The input mode supports switch debouncing or programmable external IRQ routing. The
output mode supports two sets of programmable LED blinking periods.
2.6.3.4 Super I/O Enhanced Hardware Monitor
The Super I/O Enhanced Hardware Monitor monitors three thermal inputs, VBAT
internally, and eight voltage monitor inputs. These hardware parameters are reported in
the BIOS and can be read from the BIOS Hardware Health Configuration menu.
2.6.3.5 Super I/O Fan Speed Controller
The Super I/O fan speed controller enables the system to monitor the speed of the fan.
One of the pins on the fan connector is reserved for fan speed detection and interfaced to
the fan speed controller on the Super I/O. The fan speed is then reported in the BIOS.