Rainbow Electronics DS2153Q - Manual (Page 45)

DS2153Q
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RECEIVE SIDE AC TIMING Figure 14–4
RCLK
RSER
RCHCLK
RCHBLK
RSYNC 1
RSYNC 2
RLCLK 3
RLINK 3
t
D5
t
CL
t
CH
t CP
t SU
t
D4
t
PW
t D3
t DD
MSB OF
SYSCLK
t
R t
F
t
SL
t
SH
t
SP
CHANNEL 1
t
D1
t
D2
NOTES:
1. RSYNC is in the output mode (RCR1.5=0).
2. RSYNC is in the input mode (RCR1.5=1).
3. RLCLK and RLINK only have a timing relationship to RCLK; no timing relationship between RLCLK/RLINK
and RSYNC is implied.
4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path.