Rainbow Electronics DS2153Q - Manual (Page 32)

DS2153Q
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DS2153Q JITTER ATTENUATION Figure 12–4
ITU G.7XX
PROHIBITED AREA
1 10 100 1K 10K 100K
FREQUENCY (Hz)
0 dB
–20 dB
–40 dB
–60 dB
JITTER A
TTENUA
TION
(dB)
13.0 TIMING DIAGRAMS/SYNCHRONIZATION FLOWCHART/TRANSMIT DATA FLOW
DIAGRAM
RECEIVE SIDE TIMING Figure 13–1
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FRAME# 16 1 2 3 4 5 6 14
RSYNC 1
RSYNC 2
RLCLK 3
RLINK 4
NOTES:
1. RSYNC in the frame mode (RCR1.6=0).
2. RSYNC in the multiframe mode (RCR1.6=1).
3. RLCLK is programmed to output just the Sa4 bit.
4. RLINK will always output all five Sa bits as well as the rest of the receive data stream.
5. This diagram assumes the CAS MF begins with the FAS word.