Rainbow Electronics DS2153Q - Manual (Page 13)

DS2153Q
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applied and is stable. Must be set and cleared again for a subsequent
reset. Do not leave this bit set high.
LIRST CCR3.3 Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that affects the slicer, AGC, clock recovery state machine,
and jitter attenuator. Normally this bit is only toggled on power–up. Must be
cleared and set again for a subsequent reset.
– CCR3.2 Not Assigned. Should be set to zero when written.
TSCLKM CCR3.1 Transmit Backplane Clock Select. Must be set like RCR2.2.
0 = 1.544 MHz
1 = 2.048 MHz
– CCR3.0 Not Assigned. Should be set to zero when written.
POWER–UP SEQUENCE
On power–up, after the supplies are stable, the
DS2153Q should be configured for operation by writing
to all of the internal registers (this includes the Test Reg-
isters) since the contents of the internal registers cannot
be predicted on power–up. Next, the LIRST bit should
be toggled from zero to one to reset the line interface cir-
cuitry (it will take the DS2153Q about 40 ms to recover
from the LIRST bit being toggled). Finally, after the SY-
SCLK input is stable, the ESR bit should be toggled from
a zero to a one and back to zero (this step can be
skipped if the elastic store is not being used).
4.0 STATUS AND INFORMATION
REGISTERS
There is a set of four registers that contain information
on the current real time status of the DS2153Q, Status
Register 1 (SR1), Status Register 2 (SR2), Receive
Information Register (RIR), and Synchronizer Status
Register (SSR). When a particular event has occurred
(or is occurring), the appropriate bit in one of these four
registers will be set to a one. All of the bits in these regis-
ters operate in a latched fashion (except for the SSR).
This means that if an event occurs and a bit is set to a
one in any of the registers, it will remain set until the user
reads that bit. The bit will be cleared when it is read and
it will not be set again until the event has occurred again
or if the alarm is still present.
The user will always precede a read of the SR1, SR2,
and RIR registers with a write. The byte written to the
register will inform the DS2153Q which bits the user
wishes to read and have cleared. The user will write a
byte to one of these three registers, with a one in the bit
positions he or she wishes to read and a zero in the bit
positions he or she does not wish to obtain the latest
information on. When a one is written to a bit location,
the read register will be updated with current value and it
will be cleared. When a zero is written to a bit position,
the read register will not be updated and the previous
value will be held. A write to the status and information
registers will be immediately followed by a read of the
same register. The read result should be logically
AND’ed with the mask byte that was just written and this
value should be written back into the same register to
insure that bit does indeed clear. This second write step
is necessary because the alarms and events in the sta-
tus registers occur asynchronously in respect to their
access via the parallel port. This write–read–write
scheme allows an external microcontroller or micropro-
cessor to individually poll certain bits without disturbing
the other bits in the register. This operation is key in con-
trolling the DS2153Q with higher–order software lan-
guages.
The SSR register operates differently than the other
three. It is a read only register and it reports the status of
the synchronizer in real time. This register is not latched
and it is not necessary to precede a read of this registers
with a write.
The SR1 and SR2 registers have the unique ability to
initiate a hardware interrupt via the INT1 and INT2 pins
respectively. Each of the alarms and events in the SR1
and SR2 can be either masked or unmasked from the
interrupt pins via the Interrupt Mask Register 1 (IMR1)
and Interrupt Mask Register 2 (IMR2) respectively.