Rainbow Electronics DS2153Q - Manual (Page 28)

DS2153Q
022697 28/48
DJA LICR.1 Disable Jitter Attenuator.
0=jitter attenuator enabled
1=jitter attenuator disabled
TPD LICR.0 Transmit Power Down.
0=normal transmitter operation
1=powers down the transmitter and 3–states the TTIP and TRING pins
12.1 Receive Clock and Data Recovery
The DS2153Q contains a digital clock recovery system.
See the DS2153Q Block Diagram in Section 1 and Fig-
ure 12.1 for more details. The DS2153Q couples to the
receive E1 shielded twisted pair or COAX via a 1:1
transformer. See Table 12.3 for transformer details. The
DS2153Q automatically adjusts to the E1 signal being
received at the RTIP and RRING pins and can handle
E1 twisted pair cables of 0.6 mm (22 AWG) from 0 to 1.5
KM in length. The crystal attached at the XTAL1 and
XTAL2 pins is multiplied by four via an internal PLL and
fed to the clock recovery system. The clock recovery
system uses both edges of the clock from the PLL circuit
to form a 32 times oversampler which is used to recover
the clock and data. This oversampling technique offers
outstanding jitter tolerance (see Figure 12.2).
Normally, the clock that is output at the RCLK pin is the
recovered clock from the E1 AMI/HDB3 waveform pres-
ented at the RTIP and RRING inputs. When no AMI sig-
nal is present at RTIP and RRING, a Receive Carrier
Loss (RCL) condition will occur and the RCLK can be
sourced from either the ACLKI pin or from the crystal
attached to the XTAL1 and XTAL2 pins. The DS2153Q
will sense the ACLKI pin to determine if a clock is pres-
ent. If no clock is applied to the ACLKI pin, then it should
be tied to RVSS to prevent the device from falsely sens-
ing a clock. See Table 12.1. If the jitter attenuator is
either placed in the transmit path or is disabled, the
RCLK output can exhibit short high cycles of the clock.
This is due to the highly oversampled digital clock recov-
ery circuitry. If the jitter attenuator is placed in the
receive path (as is the case in most applications), the jit-
ter attenuator restores the RCLK to being close to 50%
duty cycle. Please see the Receive AC Timing Charac-
teristics in Section 14 for more details.
SOURCE OF RCLK UPON RCL Table 12–1
ACLKI PRESENT? RECEIVE SIDE JITTER
ATTENUATOR
TRANSMIT SIDE JITTER
ATTENUATOR
yes ACLKI via the jitter attenuator ACLKI
no centered crystal TCLK via the jitter attenuator
12.2 Transmit Waveshaping and Line Driving
The DS2153Q uses a set of laser–trimmed delay lines
along with a precision Digital–to–Analog Converter
(DAC) to create the waveforms that are transmitted onto
the E1 line. The waveforms created by the DS2153Q
meet the ITU specifications. See Figure 12.3. The user
will select which waveform is to be generated by prop-
erly programming the L2/L1/L0 bits in the Line Interface
Control Register (LICR). The DS2153Q can set set up
in a number of various configurations depending on the
application. See Table 12.2 and Figure 12.1.