Rainbow Electronics DS2153Q - Manual (Page 4)

DS2153Q
022697 4/48
PIN DESCRIPTION Table 1–1
PIN SYMBOL TYPE DESCRIPTION
1
2
3
4 AD4
AD5
AD6
AD7 I/O Address/Data Bus. A 8–bit multiplexed address/data bus.
5 RD(DS) I Read Input (Data Strobe).
6 CS I Chip Select. Must be low to read or write the port.
7 ALE(AS) I Address Latch Enable (Address Strobe). A positive going edge serves to
demultiplex the bus.
8 WR(R/W) I Write Input (Read/Write).
9 RLINK O Receive Link Data. Outputs the full receive data stream including the Sa
bits. See Section 13 for timing details.
10 RLCLK O Receive Link Clock. 4 KHz to 20 KHz demand clock for the RLINK output;
controlled by RCR2. See Section 13 for timing details.
11 DVSS – Digital Signal Ground. 0.0 volts. Should be tied to local ground plane.
12 RCLK O Receive Clock. Recovered 2.048 MHz clock.
13 RCHCLK O Receive Channel Clock. 256 KHz clock which pulses high during the LSB
of each channel. Useful for parallel to serial conversion of channel data. See
Section 13 for timing details.
14 RSER O Receive Serial Data. Received NRZ serial data, updated on rising edges
of RCLK or SYSCLK.
15 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which
identifies either frame (RCR1.6=0) or multiframe boundaries (RCR1.6=1). If
the elastic store is enabled via the RCR2.1, then this pin can be enabled to be
an input via RCR1.5 at which a frame boundary pulse is applied. See Section
13 for timing details.
16 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock. A dual function output.
If TCR2.0=0, will toggle high when the synchronizer is searching for the E1
frame and multiframe; if TCR2.0=1, will toggle high if the TCLK pin has not
toggled for 5
µ s.
17 SYSCLK I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic
store functions are enabled via RCR2.1. Should be tied low in applications
that do not use the elastic store. If tied high for at least 100
µ
s, will force all
output pins (including the parallel port) to 3–state.
18 RCHBLK O Receive Channel Block. A user programmable output that can be forced
high or low during any of the 32 E1 channels. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all E1 channels
are used such as Fractional E1, 384K bps service (H0), 1920K bps (H12),
or ISDN–PRI. Also useful for locating individual channels in drop–and–insert
applications. See Section 13 for timing details.
19 ACLKI I Alternate Clock Input. Upon a receive carrier loss, the clock applied at this
pin (normally 2.048 MHz) will be routed to the RCLK pin. If no clock is routed
to this pin, then it should be tied to DVSS.