Rainbow Electronics DS2153Q - Manual (Page 2)

DS2153Q
022697 2/48
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths.
The framer locates the frame and multiframe bound-
aries and monitors the data stream for alarms. It is also
used for extracting and inserting signaling data, Si, and
Sa–bit information. The device contains a set of 71
8–bit internal registers which the user can access and
control the operation of the unit. Quick access via the
parallel control port allows a single micro to handle
many E1 lines. The device fully meets all of the latest E1
specifications including ITU G.703, G.704, G.706,
G.823, and I.431 as well as ETSI 300 011 and 300 233.
TABLE OF CONTENTS
1. Introduction
2. Parallel Control Port
3. Control and Test Registers
4. Status and Information Registers
5. Error Count Registers
6. Sa Data Link Control and Operation
7. Signaling Operation
8. Transmit Idle Registers
9. Clock Blocking Registers
10. Elastic Store Operation
11. Additional (Sa) and International (Si)
Bit Operation
12. Line Interface Control Function
13. Timing Diagrams, Synchronization Flowchart,
and Transmit flow Diagram
14. DC and AC Characteristics
1.0 INTRODUCTION
The analog AMI waveform off of the E1 line is trans-
former coupled into the RRING and RTIP pins of the
DS2153Q. The device recovers clock and data from the
analog signal and passes it through the jitter attenuation
mux to the receive side framer where the digital serial
stream is analyzed to locate the framing pattern. If
needed, the receive side elastic store can be enabled in
order to absorb the phase and frequency differences
between the recovered E1 data stream and an asynch-
ronous backplane clock which is provided at the
SYSCLK input.
The transmit side of the DS2153Q is totally independent
from the receive side in both the clock requirements and
characteristics. The transmit formatter will provide the
necessary data overhead for E1 transmission. Once
the data stream has been prepared for transmission, it is
sent via the jitter attenuation mux to the waveshaping
and line driver functions. The DS2153Q will drive the E1
line from the TTIP and TRING pins via a coupling trans-
former.
Reader’s Note
This data sheet assumes a particular nomenclature of
the E1 operating environment. There are 32 8–bit time-
slots in E1 systems which are numbered 0 to 31. Time-
slot 0 is transmitted first and received first. These 32
timeslots are also referred to as channels with a num-
bering scheme of 1 to 32. Timeslot 0 is identical to chan-
nel 1, timeslot 1 is identical to channel 2, and so on.
Each timeslot (or channel) is made up of eight bits which
are numbered 1 to 8. Bit number 1 is the MSB and is
transmitted first. Bit number 8 is the LSB and is trans-
mitted last. Throughout this data sheet, the following
abbreviations will be used:
FAS Frame Alignment Signal
CAS Channel Associated Signaling
MF Multiframe
Si International Bits
CRC4 Cyclical Redundancy Check
CCS Common Channel Signaling
Sa Additional bits
E–bit CRC4 Error bits