Xilinx LOGICORE UG144 - Manual (Page 82)

82 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 8: Configuration and Status R
-- DISCONTINUED PRODUCT --
MDIO Configuration
The register contents for the Management Configuration Word are described in Table 8-7 .
Address Filter Configuration
Table 8-8 through Table 8-12 describe the registers used to access the Address Filter
configuration when the GEMAC core implemented with an Address Filter. The register
contents for the two unicast address registers are found in
Table 8-8 and Table 8-9 .
Table 8-7: Management Configuration Word
Bits
Default
Value
Description
4-0 All 0s Clock Divide[4:0] This value enters a logical equation
which enables the mdc frequency to be set as a divided
down ratio of the host_clk frequency.
5 0 MDIO Enable When this bit is ‘1,’ the MDIO interface can
be used to access attached PHY devices. When this bit is
‘0,’ the MDIO interface is disabled and the MDIO signals
remain inactive.
31-6 n/a Reserved
Table 8-8: Unicast Address Word 0
Bits
Default
Value
Description
31-0 All 0s Address filter unicast address[31:0].
The address is ordered so the first byte received is the
lowest positioned byte in the register; for example, a MAC
address of AA-BB-CC-DD-EE-FF would be stored in
Address[47:0] as 0xFFEEDDCCBBAA.
Table 8-9: Unicast Address Word 1
Bits
Default
Value
Description
15-0 All 0s Address filter unicast address[47:32].
31-16 N/A Reserved