Xilinx LOGICORE UG144 - Manual (Page 22)

22 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 2: Core Architecture R
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Core Components
Transmit Engine
The Transmit Engine accepts Ethernet frame data from the Client Transmitter Interface,
adds the preamble field to the start of the frame, adds padding bytes (if required) to ensure
that the frame meets the minimum frame length requirements, and adds the frame check
sequence (when configured to do so). The transmitter also ensures that the inter-frame
spacing between successive frames is at least the minimum specified. The frame is then
converted into a format that is compatible with the GMII and sent to the GMII Block.
Receive Engine
The Receive Engine accepts Ethernet frame data from the GMII Block, removes the
preamble field at the start of the frame, removes padding bytes and Frame Check Sequence
(if required, and when configured to do so). The receiver also performs error detection on
the received frame using information such as the frame check sequence field, received
GMII error codes, and legal frame size boundaries.
Flow Control
The Flow Control block is designed to clause 31 of the IEEE 802.3-2005 standard. The MAC
may be configured to send pause frames and to act upon their reception. These two
behaviors can be configured independently.
Address Filter
The Address Filter checks the address of incoming frames into the receiver. If the Address
Filter is enabled, the device will not pass frames that do not contain one of a set of known
addresses to the client.
Management Interface
The optional processor-independent Management Interface has standard address, data,
and control signals. It may be used as is, or you can apply a logical shim to interface to
common bus architectures. See
Chapter 8, “Configuration and Status.”
This interface is used to access the following blocks.
•
Configuration Register After power up or reset, the client may reconfigure the core
parameters from their defaults. Configuration changes can be written at any time.
•
MDIO Interface The Management Interface is also used to access the MDIO interface
of the GEMAC core; this interface is typically connected to the MDIO port of a
physical layer device (PHY) to access its configuration and status registers. The MDIO
format is defined in IEEE802.3 clause 22.
GMII Block
This implements GMII style signaling for the physical interface of the core and is typically
attached to a physical layer device (PHY), either off-chip or internally integrated.