Xilinx LOGICORE UG144 - Manual (Page 74)

74 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 7: Using the Physical Side Interface R
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Virtex-5 Devices
Figure 7-9 shows using the physical receiver interface of the core to create an external
RGMII in a Virtex-5 device. The signal names and logic exactly match those delivered with
the example design when RGMII is selected.
Figure 7-9 also shows that the input receiver signals are registered in the IOBs in IDDR
components. These components convert the input double data rate signals into GMII
specification signals. The gmii_rx_er_int signal is derived in the FPGA fabric from the
outputs of the control IDDR component.
The IODELAY components are used to phase-shift the input RGMII clock, data and control
signals to meet the setup and hold margins. The IODELAY components are used in fixed
delay mode, where the attribute IDELAY_VALUE determines the tap delay value. An
IDELAYCTRL primitive must be instantiated for this mode of operation. See the Virtex-5
User Guide for more information on the use of IDELAYCTRL and IODELAY components.
Figure 7-9: External RGMII Receiver Logic for Virtex-5 Devices
rgmii_rxc
IBUFG
IOB LOGIC
IPAD
1-Gigabit Ethernet MAC Core
gmii_rxd_int[0]
gmii_rx_dv_int
gmii_rx_er_int
gmii_rx_clk
gmii_rxd[0]
gmii_rx_dv
gmii_rx_er
BUFG
gmii_rx_clk_bufg
gmii_rxd_int[4]
gmii_rxd[4]
IOB LOGIC
rgmii_rx_ctl
IBUF
IDDR
IPAD
Q1
D Q2
C
IOB LOGIC
rgmii_rxd[0]
IBUF
IDDR
IPAD
Q1
D
Q2
C
IODELAY
IODELAY
IODELAY