Xilinx LOGICORE UG144 - Manual (Page 133)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 133
UG144 April 24, 2009
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Appendix B
Core Verification, Compliance, and
Interoperability
The GEMAC core has been verified with extensive simulation and hardware testing.
Verification by Simulation
A highly parameterizable transaction-based test bench (not part of the core deliverables)
was used to test the core. Tests include:
• Register Access
• MDIO Access
• Frame Transmission and error handling
• Frame Reception and error handling
• Address Filtering
Hardware Verification
The GEMAC core has been tested in a variety of hardware test platforms at Xilinx to
include a variety of parameterizations, including the following.
The core has been tested with the Ethernet 1000BASE-X PCS/PMA or SGMII core from
Xilinx. This follows the architecture shown in
Figure 11-2, page 115 . A test platform was
built around these cores, including a back-end FIFO capable of performing a simple ping
function, and a test pattern generator. Software running on the embedded PowerPC®
processor was used to provide access to all configuration, status and statistical counter
registers. Version 3.0 of this core was taken to the University of New Hampshire
Interoperability Lab (UNH IOL) where conformance and interoperability testing was
performed.
The core has been tested with an external 1000BASE-T PHY device. The MAC was
connected to the external PHY device using GMII, RGMII, and SGMII (in conjunction with
the Ethernet 1000BASE-X PCS/PMA or SGMII core).
The core has been tested with the Ethernet Statistics core from Xilinx, following the
architecture show in
Figure 11-5, page 120 .