Xilinx LOGICORE UG144 - Manual (Page 23)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 23
UG144 April 24, 2009
Core Interfaces R
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Core Interfaces
GMAC Core with Optional Management Interface
Figure 2-2 shows the pinout for the GEMAC core using the optional Management
Interface. The interface is unchanged, regardless of whether the optional Address Filter is
included.
Figure 2-2: Component Pinout for MAC with Optional Management Interface
gtx_clk
gmii_rx_clk
mdc
mdio_in
gmii_rxd[7:0]
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
tx_data[7:0]
tx_ack
tx_underrun
pause_req
pause_val[15:0]
host_clk
host_opcode[1:0]
host_addr[9:0]
host_wr_data[31:0]
host_rd_data[31:0]
host_miim_sel
host_req
host_miim_rdy
reset
rx_data[7:0]
rx_good_frame
rx_bad_frame
tx_data_valid
rx_data_valid
gmii_rx_dv
gmii_rx_er
gtx_clk domain
gmii_rx_clk domain
host_clk domain
tx_ifg_delay[7:0]
tx_statistics_vector[31:0]
tx_statistics_valid
rx_statistics_vector[27:0]
rx_statistics_valid
mdio_out
mdio_tri
Client Side Interface Physical Side Interface (GMII)