Xilinx LOGICORE UG144 - Manual (Page 33)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 33
UG144 April 24, 2009
Output Generation R
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Output Generation
The output files generated from the CORE Generator tool are placed in the CORE
Generator project directory. The list of output files includes the following items.
•
Netlist file for the core
•
Supporting CORE Generator files
•
Release notes and documentation
•
Subdirectories containing an HDL example design
•
Scripts to run the core through the back-end tools and to simulate the core using either
Mentor Graphics ModelSim, Cadence IUS or Synopsys VCS simulators.
See the 1-Gigabit Ethernet MAC Getting Started Guide for more information about the CORE
Generator output files and for details on the HDL example design.
Table 3-1: XCO File Values and Default Values
Parameter XCO File Values Default GUI Setting
component_name ASCII text starting with a letter and
based upon the following character
set: a..z, 0..9 and _ gig_eth_mac_v8_5
physical_interface One of the following keywords: gmii,
rgmii gmii
management_interface One of the following keywords: true,
false true
address_filter One of the following keywords: true,
false true
no_of_address_table_
entries
Integer in the range 0 - 4 4