Xilinx LOGICORE UG144 - Manual (Page 75)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 75
UG144 April 24, 2009
Implementing External RGMII R
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RGMII Inband Status Decoding Logic
The inband status decoding logic is common to all device families. Figure 7-10 illustrates
the decoding of RGMII inband status information. This information is received through
the RGMII interface between frames. The signal names and logic shown exactly match
those delivered with the example design when the RGMII is selected.
Figure 7-10: RGMII Inband Status Decoding Logic
1-Gigabit Ethernet MAC Core
gmii_rx_dv_reg
gmii_rx_er_reg
gmii_rx_clk
gmii_rx_dv
gmii_rx_er
RGMII RECEIVER LOGIC
gmii_rx_clk_bufg
gmii_rxd_reg[3]
gmii_rxd[3]
gmii_rxd_reg[2]
gmii_rxd[2]
gmii_rxd_reg[1]
gmii_rxd[1]
gmii_rxd_reg[0]
gmii_rxd[0]
OBUF
OPAD
inband_link_status
D Q
D Q
D Q
D Q
CE
CE
CE
CE
OBUF
OPAD
inband_clock_speed[0]
OBUF
OPAD
inband_clock_speed[1]
OBUF
OPAD
inband_duplex_status